1. Field of the Invention
The present invention relates to a mounting configuration of an electronic component and more particularly to the electronic component mounting configuration in which an electronic component chip having a plurality of protrusion-shaped electrodes arranged so as to be distributed on an entire mounting surface of the electronic component chip is mounted through protrusion-shaped electrodes onto a printed circuit board.
2. Description of the Related Art
In an integrated circuit being representative of an electronic component embedded in various electronic devices, when a semiconductor chip is mounted onto a printed circuit board, in order to meet the need for higher functionality and miniaturization of electronic devices, it is desirable that the semiconductor chip is electrically and mechanically connected to the printed circuit board in a state where more electrode terminals are integrated on a smaller-area mounting surface of the semiconductor chip. To satisfy such a requirement, a mounting configuration of the integrated circuit employing a flip chip method is disclosed in which the semiconductor chip is mounted by arranging protrusion-shaped electrodes made up of solder bumps serving as electrode terminals on an entire mounting surface of the semiconductor chip, instead of arranging the protrusion-shaped electrodes only in portions surrounding the mounting surface of the semiconductor chip.
FIGS. 5A and 5B are diagrams showing a related mounting configuration of an electronic component using the flip chip method; FIG. 5A is a plan view schematically showing configurations of a rear surface of a semiconductor chip and FIG. 5B is a cross-sectional view showing the mounting configuration of FIG. 5A taken along a line B-B. In the electronic component mounting configuration, as shown in FIGS. 5A and 5B, the semiconductor chip 102 in which a plurality of solder bumps (protrusion-shaped electrodes) 101 is arranged in two-dimensional directions (X and Y directions) at equal intervals with a pitch of “P” so as to be distributed on an entire mounting surface of the semiconductor chip 102 electrically and mechanically connected through solder bumps 101 to a printed circuit board 103.
However, in the related electronic component mounting configuration 100 as shown above, the semiconductor chip 102, while an electronic device having an embedded electronic component is operating, generates heat, which is transferred through the solder bumps 101 to the printed circuit board 103, resulting in a rise of a temperature of the entire mounting configuration of the electronic component. When such a rise of the temperature occurs, due to a difference in thermal expansion coefficient between the semiconductor chip 102 and the printed circuit board 103, each of the solder bumps 101 sandwiched between the solder bumps 101 and the printed circuit board 103 receives a load in a shearing direction, thus causing the occurrence of thermal stress (hereafter simply “stress”) in each of the solder bumps 101. If the solder bumps 101 are arranged at equal intervals on the mounting surface of the semiconductor chip 102 as described above, the larger stress occurs in the solder bumps 101, in particular, arranged from a central portion of the semiconductor chips 102 toward a peripheral portion thereof and, therefore, the occurrence of thermal fatigue breakdown starts from the solder bumps 101 arranged in the outermost portion of the semiconductor chips 102. This results in lowering of the reliability of electronic components.
To solve this problem, an electronic component mounting configuration capable of relieving stress occurring in solder bumps by providing a contrivance to distribute solder bumps arranged in a semiconductor chip is disclosed (Patent Reference 1: Japanese Utility Model Laid-open No. Hei 03-016327). In the disclosed electronic component mounting configuration 200 as shown in FIGS. 7A and 7B, a pitch among solder bumps 201A arranged in portions at four corners of the semiconductor chip 202 is set to be P12 and a pitch P11 between a solder bump arranged in a central portion of the semiconductor chip 202 and the solder bumps 201A is smaller than the P12 (P11>P12). By configuring as above, concentration of stress on one solder bump in portions at four corners of the semiconductor chip 202 can be avoided and, therefore, stress can be dispersed and relieved.
Also, a mounting configuration of integrated circuits is disclosed (Patent Reference 2: Japanese Patent Application Laid-open No. 2002-246404) in which, in order to uniform stress applied to protrusion electrodes when a semiconductor chip is pressed through the protrusion-shaped electrodes on a printed circuit board with pressure, the protrusion-shaped electrodes are arranged so that an entire area of the protrusion-shaped electrodes meets specified conditions. Also, another mounting configuration of integrated circuits is disclosed (Patent Reference 3: Japanese Patent Application Laid-open No. 2002-270723) in which, in order to prevent the degradation in electrical performance, lowering of reliability, decrease in manufacturing yield, increase in manufacturing costs, the distribution density of protrusion electrode groups arranged in a mounting surface of a semiconductor chip is set so as to be highest in columns near to a central portion of the semiconductor chip and to be lower in columns outside therefrom. Also, still another mounting configuration of integrated circuits is disclosed which is capable of improving reliability by taking a potential difference among protrusion-shaped electrodes arranged on an mounting surface of a semiconductor chip (Patent Reference 4: Japanese Patent Application Laid-open No. 2005-243913). Still another mounting configuration of integrated circuits is disclosed which is so configured to set a distribution density of protrusion-shaped electrodes at a specified value in order to decrease the occurrence of a short circuit among protrusion-shaped electrodes arranged on a mounting surface of a semiconductor chip (Patent Reference 5: Japanese Patent Application Laid-open No. Hei 10-004125).
However, these related mounting configurations have problems. That is, in the integrated circuit mounting configuration disclosed in the Patent Reference 2, the stress imposed on protrusion-shaped electrodes when the semiconductor chip is mounted with pressure is made to become a problem, while the stress occurring in the protrusion-shaped electrodes at the time of rising of temperatures when the integrated-circuits are operating as in the case of the present invention is not made to become a problem. In the mounting configuration of integrated circuits disclosed in the Patent Reference 3, the distribution density of protrusion electrode groups formed on the mounting surface of the semiconductor chip is set so as to become highest in columns near to a central portion of the semiconductor chip and to become lower in columns toward the outside, however, this arrangement is reverse to that employed in the present invention in which each protrusion-shaped electrode is formed so that the density of the distribution of the protrusion-shaped electrodes becomes the higher from a central portion of the mounting surface of the semiconductor chip toward a peripheral portion thereof. In the mounting configuration of integrated circuits disclosed in the Patent Reference 4, the protrusion-shaped electrodes are arranged by taking a potential difference among the protrusion-shaped electrodes into consideration in order to improve quality, however, the object of the present invention that stress occurring in protrusion-shaped electrodes at the time of rising of temperatures of an electronic component is made uniform is not sought in the related configuration. In the mounting configuration of integrated circuits disclosed in the Patent Reference 5, a distribution density of protrusion-shaped electrodes is set at a specified value in order to decrease the occurrence of a short circuit among protrusion-shaped electrodes arranged on the mounting surface of the semiconductor chip, however, the object and means disclosed in the Patent Reference 5 are different from those employed by the prevent invention.
The mounting configuration of integrated circuits disclosed in the Patent Reference 1 has the following problem. That is, the object of the semiconductor chip 202 in which the solder bumps 201 serving as protrusion-shaped electrodes are arranged only in portions surrounding the mounting surface is to relieve the stress occurring in the solder bumps formed as above. There occurs a difference in stress occurring in the protrusion-shaped electrodes at the time of rising of temperatures during operations of the integrated circuits between the semiconductor chip on which such solder bumps are arranged only in portions surrounding the mounting surface and the semiconductor chip on which the solder bumps are arranged so as to be distributed on the entire mounting surface of the semiconductor chip. Therefore, the means for solving the problem employed in the Patent Reference 1 can not be applied, as it is, to the mounting configuration of the present invention in which solder bumps are distributed all over the entire mounting surface of the semiconductor chip.